library verilog;
use verilog.vl_types.all;
entity wbs_mem is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        adr_i           : in     vl_logic_vector(31 downto 0);
        dat_i           : in     vl_logic_vector(31 downto 0);
        dat_o           : out    vl_logic_vector(31 downto 0);
        we_i            : in     vl_logic;
        sel_i           : in     vl_logic_vector(3 downto 0);
        cyc_i           : in     vl_logic;
        stb_i           : in     vl_logic;
        ack_o           : out    vl_logic;
        err_o           : out    vl_logic;
        rty_o           : out    vl_logic
    );
end wbs_mem;
